1. Field of the Invention
This invention relates to a method and apparatus for independently controlling and implementing the reset of the processors and cache memory system controllers in multiple processor computer systems utilizing cache memory.
2. Discussion of the Related Art
Personal computer systems have developed from systems utilizing a single processing unit or CPU to systems which include multiple processors operating in parallel. One of the first developments was to include a second arithmetic coprocessor in parallel with the main CPU to perform time-consuming and complex arithmetic tasks leaving the main CPU free to perform system control, input/output, memory operations and other less time-consuming code execution. Systems incorporating the Intel 80386 processor and 80387 coprocessor are one common example of such more advanced systems.
In addition to the development of arithmetic coprocessors, memory systems used by the processor have evolved from single units of read only memory for storing fixed system instructions and static random access integrated circuit memory to further include peripheral memory devices such as floppy-disk and fixed-disk memories and associated interface and control circuitry.
As the speed of processors was enhanced, it became necessary to enhance the speed at which memory operations could be performed so as to take advantage of the newer high speed processors such as the Intel 80386. High speed static RAM devices were available, but to implement the entire memory requirement with high speed RAM was too expensive for personal computer systems. One solution to the problem was the implementation of what is known as a cache memory system.
In a cache memory system a small amount of more expensive fast memory, typically static RAM devices, is used for high speed execution and slower, less expensive dynamic RAM and peripheral devices are used for the bulk memory requirements. Data or code contained in portions of the main memory is duplicated in the fast cache memory so that operations requiring only data or code in cache memory can be executed quickly. Idealized cache memory systems seek to match the upcoming processor code and data requests to code and data maintained in cache memory by changing the contents of the cache memory as the processor executes code or instructions to minimize the number of times slower memory has to be accessed by the processor.
Updating and maintaining the directory to the cache memory is performed by a device known as a cache controller. One such device is the Intel 82385 cache controller designed for use with the 80386 processor. The cache controller also determines whether the requested data or code is resident in cache or whether it is necessary to retrieve it for the processor from main memory. The cache controller therefore interfaces between the processor and the cache memory and the main memory via one or more system busses. Details of an example of such systems is set forth in the Intel system design handbook for the 80386 family, such as the Microprocessor and Peripheral Handbook Volume 1, specifically pages 4-292 through 4-353 of the October, 1988 reference manual.
Further development of personal computer systems led to the design of systems including multiple processors, each having an associated cache memory and cache controller, as well as a coprocessor. In such systems one of the processors is typically the primary processor which controls and utilizes the other secondary processors. The Intel Microprocessor and Peripheral Handbook at page 4-295 disclosed such a multiple processor system where each processor and associated cache system were connected to a common local bus which is then connected to a system bus. In the Intel design, another device known as the Intel 82380 32-bit DMA controller was also connected to the local bus and utilized to provide direct memory access control, interrupt control, timing, wait state generation, dynamic (non-cache) memory refreshing and processor reset control. In the Intel system, both processors and cache controllers interface to the system bus via a common local bus interface. As designed, the cache controllers and associated processors were reset by a common signal.
Resets are utilized to interrupt all system activity and bring all elements of the system to a known initialization state. Resets are assigned the highest priority among system signals and when a reset signal is asserted, all activity ceases. In 80386 and earlier 80286 based systems reset signals can be generated by hardware such as a switch, by operator command via a keyboard or under program control. A hardware reset occurs when the system is first energized or turned on. Software or program controlled resets are utilized by programmers for a variety of reasons.
One example of the use of a programmed reset relates to setting the mode of the processor. Both 80286 and 80386 processors are initialized in a mode known as the Real Mode. Real Mode operation is typically only utilized as a prelude to system operation such as during a system initialization sequence which occurs on power up. Real Mode operation utilizes a system addressing scheme which is limited and greatly restricts the ability of the processor to address large memory spaces. In the 80386 Real Mode operation limits the processor to one megabyte of addressable memory space. Typically, once initialization is completed, the system transitions to Protected Mode. Protected Mode allows the processor to use virtual addressing to expand the addressable memory to four terabytes.
In the design of the 80286 family it was not anticipated that after system initialization it would be desirable to revert from Protected Mode to Real Mode, and consequently no provision was made to accomplish this under program control. Software designed for the 80286 system frequently incorporated software initiated resets to cause the 80286 to reset in order to revert from Protected Mode to Real Mode. In order to maintain software compatibility with software designed for 80286 systems, it is necessary to accommodate software resets as a method of resetting the processor to Real Mode.
In prior art systems using multiple processors and cache controllers connected via a common bus the utilization of a reset signal caused all processors and cache controllers to reset. On reset the 82385 cache controller clears the cache memory by executing a cache flush operation which invalidates all data stored in the cache. When 82385 controllers are utilized in master mode, a reset causes the controller to latch the 80386 reset values to the system bus interface by emitting a pulsed output signal on its address clock pulse (BACP) output pin. This results in the 82385 trying to acquire control of the system bus. In situations where the reset is a software reset intended only to reset one processor, as distinguished from a power up, hardware system reset, the prior art provided no simple and efficient way to avoid bus contention by the 82385 controllers which tried to acquire the bus while one of the non-reset processors was operating. In multiprocessor systems, it is desirable to independently reset each processor. The prior art provides no suitable mechanism to meet this need.
The present invention addresses these shortcomings of prior art systems and provides a system wherein each processor may be reset independently under program control after system initialization. The present invention also provides a system for resetting each processor independently without introducing cache memory incoherency. A cache memory incoherency may occur when more than one device has access to common memory space. In such situations, one device may make an alteration to data in memory which is not also made to the duplicated data in the cache memory.
The present invention provides a system of independently resetting processors in a multiprocessor cache memory environment. On power up, a hardware reset, all processors and cache memory devices are reset to initialization values. The cache controllers are reset only on hardware reset, and placed in a hold state after the processor reset signals are released. Since power up resets of the processors and cache controllers are synchronized, no bus contention results. After hardware reset, when the secondary processors acknowledge a hold request, the primary processor is given access to the common processor or host bus until system protocol determines one of the other processors or system elements, such as the extended industry standard (EISA) bus in EISA systems, requires the bus.
Software or programmed resets cause only the selected processor(s) and not the cache controllers to be reset. Programmed resets are synchronized to hold acknowledge signals from the processors so that resets do not occur during program execution by one or more processors thereby avoiding any cache memory incoherency. The primary processor can be reset under program control consistent with existing software convention without effecting the operation of the cache controllers or the secondary processors. The primary processor may also be independently reset in response to a keyboard initiated instruction. The secondary processors can be program reset by setting a reset bit located in a designated secondary processor control register addressable under program control, or via the user interface keyboard, or by the primary processor. All processors are reset in response to system shutdown signals.